Table of Contents
1. Combinational Logic
1.1 Electronics and digital systems
1.2 Gates
1.3 Boolean algebra and equations
1.4 Digital circuit simulator
1.5 Timing diagrams
1.6 Equations to/from circuits
1.7 Basic circuit drawing conventions
1.8 Basic properties of Boolean algebra
1.9 Sum-of-products form
1.10 Sum-of-minterms form
1.11 Binary and counting
1.12 Truth tables
1.13 Product-of-sums form and maxterms
1.14 Top-down design + examples
1.15 Why study digital design
1.16 Multiple outputs
2. Combinational Logic II
2.1 Two-level combinational logic simplification
2.2 K-maps: Introduction
2.3 3- and 4-variable K-maps
2.4 K-map examples
2.5 DeMorgan’s Law
2.6 XOR / XNOR gates
2.7 NAND / NOR (universal gates)
2.8 Muxes
2.9 Decoders
2.10 Encoders
2.11 Don’t cares
2.12 Prime implicants and minimal covers
2.13 Quine-McCluskey
3. Sequential Logic
3.1 SR latches
3.2 Clocks, D flip-flops, and registers
3.3 FSMs
3.4 FSM simulator
3.5 Capturing behavior with FSMs
3.6 FSM examples
3.7 FSMs to circuits (design)
3.8 Reducing states
3.9 State encodings
3.10 Mealy FSMs
3.11 FSM issues
3.12 Controller clock frequency
3.13 Circuits to FSMs (analysis)
4. Datapath Components
4.1 Adders
4.2 Signed numbers in binary
4.3 Subtractors
4.4 Comparators
4.5 N-bit muxes
4.6 Load registers
4.7 Shifters
4.8 Counters and timers
4.9 Multipliers (array-style)
5. RTL Design
5.1 HLSMs: Introduction
5.2 HLSMs with variables
5.3 HLSMs with a loop
5.4 HLSM simulator
5.5 Capturing behavior with HLSMs
5.6 Datapaths for HLSMs
5.7 HLSMs to circuits: RTL design
5.8 RTL timing
5.9 Assigning and reading variables
6. Datapath Components II
6.1 Tradeoffs
6.2 Carry-lookahead adders
6.3 Register files
6.4 Multi-function registers
6.5 ALUs
6.6 SRAM and DRAM
6.7 RAM design
6.8 ROM design
6.9 Queues (FIFOs)
6.10 Chip economics
6.11 Composing memory
7. Verilog HDL
7.1 Introduction to HDLs (Verilog)
7.2 Combinational logic (Verilog)
7.3 Identifiers (Verilog)
7.4 Testbench (Verilog)
7.5 Sequential logic (Verilog)
7.6 Datapath components: Structural (Verilog)
7.7 RTL design (Verilog)
7.8 Datapath components: Behavioral (Verilog)
8. VHDL
8.1 Introduction to HDLs (VHDL)
8.2 Combinational logic (VHDL)
8.3 Identifiers (VHDL)
8.4 Testbench (VHDL)
8.5 Sequential logic (VHDL)
8.6 Datapath components: Structural (VHDL)
8.7 RTL design (VHDL)
8.8 Datapath components: Behavioral (VHDL)
9. Appendix: Information as Bits
9.1 ASCII and Unicode
9.2 Unsigned binary numbers
9.3 Signed binary numbers: Two’s complement
9.4 Binary, hexadecimal, and octal
9.5 General number bases
9.6 Floating-point numbers
9.7 Floating-point arithmetic
9.8 Arrays
9.9 Graphics
9.10 Image and video data
9.11 Audio
9.12 Naming numerous bits
10. Additional Material
10.1 Gray code
10.2 JK and T latches and flip-flops
A hands-on approach to teaching Digital Design that combines theory and practice
Digital Design emphasizes a top-down behavior-to-circuits perspective, for combinational, sequential, and high-level (register-transfer-level) design. The book’s HDL (Verilog and VHDL) coverage is intentionally template-focused, teaching just enough of the HDLs to understand the templates. Includes:
- Web-based simulators, including circuit, finite-state machine, high-level state machine, and datapath simulators
- Hands-on learning tools, including Boolean algebra solver, K-map minimizer, state machine capture, and more
- Hundred of participation activities, including questions, animations and auto-graded challenge activities
- Adopters have access to a test bank with questions for every chapter
Ideal book for a traditional “what’s under the hood” goal, as well as for an introduction to embedded systems. Now with Verilog labs!
Emphasis on RTL design
Director of Content Authoring and Research Dr. Yamuna Rajasekhar explains how the Digital Design zyBook provides students with a crucial, real-world understanding of RTL design:
What is a zyBook?
Digital Design is a web-native, interactive zyBook that helps students visualize concepts to learn faster and more effectively than with a traditional textbook. (Check out our research.)
Since 2012, over 1,700 academic institutions have adopted digital zyBooks to transform their STEM education.
zyBooks benefit both students and instructors:
- Instructor benefits
- Customize your course by reorganizing existing content, or adding your own content
- Continuous publication model updates your course with the latest content and technologies
- Robust reporting gives you insight into students’ progress, reading and participation
- Save time with auto-graded labs and challenge activities that seamlessly integrate with your LMS gradebook
- Build quizzes and exams with hundreds of included test questions
- Student benefits
- Learning questions and other content serve as an interactive form of reading
- Instant feedback on labs and homework
- Concepts come to life through extensive animations embedded into the interactive content
- Review learning content before exams with different questions and challenge activities
- Save chapters as PDFs to reference the material at any time
FSM Simulator Tool
In this video, zyBooks’ Dr. Rajasekhar demonstrates how the FSM Simulator tool works in Digital Design:
Authors
Frank Vahid
Computer Science PhD, Univ. of California, Irvine / zyBooks Co-Founder
Roman Lysecky
Professor Emeritus of Electrical and Computer Engineering, Univ. of Arizona
